US 12,136,612 B2
Three-dimension large system integration
Chen-Hua Yu, Hsinchu (TW); and Tin-Hao Kuo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 4, 2022, as Appl. No. 17/657,843.
Application 17/657,843 is a division of application No. 16/671,927, filed on Nov. 1, 2019, granted, now 11,296,062.
Claims priority of provisional application 62/866,227, filed on Jun. 25, 2019.
Prior Publication US 2022/0223572 A1, Jul. 14, 2022
Int. Cl. H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/105 (2013.01) [H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
bonding a plurality of device dies to an interposer wafer;
encapsulating the plurality of device dies in a first encapsulant;
polishing the interposer wafer to reveal through-vias in a substrate of the interposer wafer;
forming electrical connectors connecting to the through-vias;
singulating the interposer wafer and the first encapsulant to form a first building block;
encapsulating the first building block in a second encapsulant;
forming a fan-out interconnect structure over and contacting the second encapsulant; and
attaching a power module over the fan-out interconnect structure.