US 12,136,609 B2
Semiconductor device and method of manufacture
Haohua Zhou, Fremont, CA (US); Mei Hsu Wong, Saratoga, CA (US); and Tze-Chiang Huang, Saratoga, CA (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,282.
Application 18/344,282 is a continuation of application No. 17/135,312, filed on Dec. 28, 2020, granted, now 11,735,565.
Claims priority of provisional application 63/059,234, filed on Jul. 31, 2020.
Prior Publication US 2023/0343754 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/525 (2006.01); H03K 5/24 (2006.01); H03K 19/20 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 23/5256 (2013.01); H03K 5/24 (2013.01); H03K 19/20 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
receiving a first semiconductor device, the first semiconductor device comprising:
a first unique identifier structure;
a first electrical input; and
a first comparator comprising a first input connected to the first unique identifier structure and comprising a second input connected to the first electrical input;
a first AND gate comprising:
a fifth input connected to the first comparator; and
a sixth input connected to an external connector of the first semiconductor device;
receiving a second semiconductor device, the second semiconductor device comprising:
a second unique identifier structure different from the first unique identifier structure;
a second electrical input electrically connected to the first electrical input; and
a second comparator comprising a third input connected to the second unique identifier structure and comprising a fourth input connected to the second electrical input; and
bonding the first semiconductor device to the second semiconductor device.