US 12,136,607 B2
Semiconductor devices including stacked dies with interleaved wire bonds and associated systems and methods
Koichi Kawai, Yokohama (JP); Raj K. Bansal, Boise, ID (US); Takehiro Hasegawa, Yokohama (JP); and Chang H. Siau, Saratoga, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 11, 2022, as Appl. No. 17/718,217.
Claims priority of provisional application 63/239,457, filed on Sep. 1, 2021.
Prior Publication US 2023/0061258 A1, Mar. 2, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H10B 41/41 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 24/47 (2013.01); H01L 25/50 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49107 (2013.01); H01L 2224/4911 (2013.01); H01L 2224/49174 (2013.01); H10B 41/41 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a memory controller electrically coupled to the substrate, wherein the memory controller includes a first in/out (I/O) channel and a second I/O channel;
a plurality of first memories and second memories arranged in a stack, wherein the first memories are interleaved between the second memories in the stack;
a plurality of first wire bonds electrically coupling the first memories to the first I/O channel of the memory controller via the substrate; and
a plurality of second wire bonds electrically coupling the second memories to the second I/O channel of the memory controller via the substrate.
 
10. A memory device, comprising:
a substrate;
a memory controller electrically coupled to the substrate, wherein the memory controller includes a first in/out (I/O) channel and a second I/O channel;
a plurality of first memories of a first type coupled to the substrate;
a plurality of second memories of a second type coupled to one or more of the first memories and arranged in a stack; and
a plurality of wire bonds electrically coupling the second memories to the memory controller via the substrate, wherein alternating ones of the second memories are electrically coupled to the first I/O channel or the second I/O channel of the memory controller.