US 12,136,603 B2
Semiconductor arrangement comprising a semiconductor element, a substrate and bond connecting means
Bernd Kürten, Obermichelbach (DE); and Felix Zeyss, Erlangen (DE)
Assigned to Siemens Aktiengesellschaft, Munich (DE)
Appl. No. 18/579,130
Filed by Siemens Aktiengesellschaft, Munich (DE)
PCT Filed Jun. 13, 2022, PCT No. PCT/EP2022/065945
§ 371(c)(1), (2) Date Jan. 12, 2024,
PCT Pub. No. WO2023/285046, PCT Pub. Date Jan. 19, 2023.
Claims priority of application No. 21185247 (EP), filed on Jul. 13, 2021.
Prior Publication US 2024/0266312 A1, Aug. 8, 2024
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/45 (2013.01) [H01L 24/43 (2013.01); H01L 24/46 (2013.01); H01L 2224/46 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48101 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor arrangement, comprising:
a substrate;
a semiconductor element connected to the substrate and comprising on a side remote from the substrate a contact surface; and
bond connecting means, with the contact surface of the semiconductor element being connected to the substrate via a first one of the bond connecting means such that the first one of the bond connecting means forms on the contact surface a stitch contact arranged between a first loop and a second loop of the first one of the bond connecting means, with the first loop having a first maximum and the second loop having a second maximum,
wherein a second one of the bond connecting means has a first transverse loop arranged to run above the first stitch contact and, viewed running parallel to the contact surface, between the first maximum of the first loop and the second maximum of the second loop, the first transverse loop of the second one of the bond connecting means being arranged to run below the first maximum of the first loop and/or the second maximum of the second loop.