US 12,136,599 B2
Three-dimensional memory devices and fabricating methods thereof
He Chen, Hubei (CN); Shu Wu, Hubei (CN); Zhen Pan, Hubei (CN); Siping Hu, Hubei (CN); Yi Zhao, Hubei (CN); and Ziqun Hua, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Feb. 2, 2022, as Appl. No. 17/591,429.
Claims priority of application No. 202110142144.0 (CN), filed on Feb. 2, 2021.
Prior Publication US 2022/0246544 A1, Aug. 4, 2022
Int. Cl. H01L 29/788 (2006.01); H01L 23/00 (2006.01); H01L 23/535 (2006.01); H01L 23/58 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01)
CPC H01L 23/562 (2013.01) [H01L 23/535 (2013.01); H01L 23/564 (2013.01); H01L 23/585 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/351 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a wafer structure having a sealing region and a chip region, comprising:
a substrate;
a memory string array over a first side of the substrate in the chip region;
a first protection structure and a second protection structure on the first side of the substrate in the sealing region;
a first contact and a second contact extending through the substrate in the sealing region,
wherein the first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure; and
an insulating structure extending through the substrate in the sealing region.