CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01)] | 11 Claims |
1. A method of manufacturing a semiconductor structure, comprising:
forming a dielectric layer over a substrate;
forming an opening in the dielectric layer;
forming a first liner conformal to the opening;
forming a porous layer in the opening and surrounded by the first liner;
forming a conductive via penetrating the dielectric layer; and
forming a conductive pad over the dielectric layer, wherein the conductive pad covers the porous layer and the conductive via.
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