US 12,136,583 B2
Method of forming a chip package, method of forming a semiconductor arrangement, chip package, and semiconductor arrangement
Chee Yang Ng, Muar (MY)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Nov. 5, 2021, as Appl. No. 17/519,805.
Claims priority of application No. 102020129148.5 (DE), filed on Nov. 5, 2020.
Prior Publication US 2022/0139798 A1, May 5, 2022
Int. Cl. H01L 23/34 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01)
CPC H01L 23/373 (2013.01) [H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3672 (2013.01); H01L 23/4334 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a semiconductor chip;
an elastic thermal interface material over the semiconductor chip, wherein the elastic thermal interface material is configured to transfer heat from the semiconductor chip to an outside;
a packaging material around the elastic thermal interface material and at least partially around the semiconductor chip; and
a gap between the elastic thermal interface material and the packaging material that is arranged directly above and extends along an upper surface of the semiconductor chip,
wherein the elastic thermal interface material extends above a surface level of the packaging material.