US 12,136,575 B2
Semiconductor package
Tomohiro Maegawa, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Appl. No. 17/600,786
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
PCT Filed Aug. 20, 2019, PCT No. PCT/JP2019/032474
§ 371(c)(1), (2) Date Oct. 1, 2021,
PCT Pub. No. WO2021/033269, PCT Pub. Date Feb. 25, 2021.
Prior Publication US 2022/0181220 A1, Jun. 9, 2022
Int. Cl. H01L 23/10 (2006.01); H01L 23/00 (2006.01); H01L 23/04 (2006.01)
CPC H01L 23/10 (2013.01) [H01L 23/04 (2013.01); H01L 23/562 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a semiconductor substrate;
a device formed on a main surface of the semiconductor substrate;
a passivation film covering the main surface;
a metallized pattern formed on the passivation film and surrounding the device;
a sealing metal layer formed on the metallized pattern and including a corner portion in a planar view;
a lid bonded to the metallized pattern with the sealing metal layer interposed therebetween and vacuum-sealing the device;
a dummy wiring formed at least between an outer portion of the corner portion of the sealing metal layer and the semiconductor substrate, softer than the metallized pattern, and not electrically connected to the device; and
a wiring formed on the main surface of the semiconductor substrate to extend under the sealing metal and electrically connect to the device, wherein
the dummy wiring does not intersect with the wiring in a plan view.
 
7. A semiconductor package comprising:
a semiconductor substrate;
a device formed on a main surface of the semiconductor substrate;
a plurality of wirings formed on the main surface of the semiconductor substrate;
a passivation film covering the main surface and the plurality of wirings;
a metallized pattern formed on the passivation film and surrounding the device;
a sealing metal layer formed on the metallized pattern; and
a lid bonded to the metallized pattern with the sealing metal layer interposed therebetween and vacuum-sealing the device,
wherein the plurality of wirings are softer than the metallized pattern, and
a width of a region where the plurality of wirings does not exist in an outer peripheral portion and an inner peripheral portion of the sealing metal layer is 0.6 times or less a thickness of the sealing metal layer.
 
11. A semiconductor package comprising:
a semiconductor substrate;
a device formed on a main surface of the semiconductor substrate;
a plurality of wirings including a wiring connected to the device and a dummy wiring not connected to the device formed on the main surface of the semiconductor substrate and;
a passivation film covering the main surface and the plurality of wirings;
a metallized pattern formed on the passivation film and surrounding the device;
a sealing metal layer formed on the metallized pattern; and
a lid bonded to the metallized pattern with the sealing metal layer interposed therebetween and vacuum-sealing the device,
wherein the plurality of wirings are arranged parallel to each other and positioned to extend alongside an outer periphery of the sealing metal layer in an outer peripheral portion of the sealing metal layer.