US 12,136,573 B2
Fabrication of a vertical fin field effect transistor with reduced dimensional variations
Kangguo Cheng, Schenectady, NY (US)
Assigned to Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed on Sep. 7, 2023, as Appl. No. 18/243,501.
Application 15/798,886 is a division of application No. 15/627,927, filed on Jun. 20, 2017, granted, now 10,014,222, issued on Jul. 3, 2018.
Application 18/243,501 is a continuation of application No. 18/087,697, filed on Dec. 22, 2022, granted, now 11,784,095.
Application 18/087,697 is a continuation of application No. 17/306,669, filed on May 3, 2021, granted, now 11,574,844, issued on Feb. 7, 2023.
Application 17/306,669 is a continuation of application No. 16/234,974, filed on Dec. 28, 2018, granted, now 10,998,240, issued on May 4, 2021.
Application 16/234,974 is a continuation of application No. 15/798,886, filed on Oct. 31, 2017, granted, now 10,204,835, issued on Feb. 12, 2019.
Application 15/627,927 is a continuation of application No. 15/199,352, filed on Jun. 30, 2016, granted, now 9,768,072, issued on Sep. 19, 2017.
Prior Publication US 2024/0249980 A1, Jul. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); H01L 21/266 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01); H10B 12/00 (2023.01)
CPC H01L 21/823487 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 21/266 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/76232 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 27/088 (2013.01); H01L 29/0603 (2013.01); H01L 29/66666 (2013.01); H01L 29/66795 (2013.01); H01L 29/6681 (2013.01); H01L 29/7827 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H10B 10/12 (2023.02); H10B 12/36 (2023.02)] 22 Claims
OG exemplary drawing
 
1. A method of forming fin pattern regions on a substrate of an integrated circuit, the method comprising:
forming a first fin pattern region, wherein a first integrated circuit component formed on the substrate comprises the first fin pattern region;
forming an adjacent second fin pattern region, wherein a second integrated circuit component formed on the substrate comprises the second fin pattern region;
forming a dummy fin in a pattern region gap between the first and second fin pattern regions, wherein
the first fin pattern region comprises an active fin comprising a first semiconductor material; and
the dummy fin comprises a second semiconductor material different from the first semiconductor material; and
removing the dummy fin.