| CPC H01L 21/823437 (2013.01) [H01L 21/28123 (2013.01); H01L 21/823431 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/28088 (2013.01); H01L 21/31058 (2013.01); H01L 21/31144 (2013.01); H01L 29/517 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate having therein a channel region;
a dielectric layer overlying the substrate, the dielectric layer having therein a trench overlying the channel region;
a gate dielectric extending along the channel region and extending partially up sidewalls of the trench;
a conductive work function layer on the gate dielectric and extending partially up sidewalls of the trench;
a gate electrode on the conductive work function layer and partially filling the trench, a topmost surface of the gate electrode being below a topmost surface of the dielectric layer and sidewalls of the gate electrode being spaced apart from respective sidewalls of the trench, wherein the topmost surface of the gate electrode deviates in height, relative to an uppermost surface of the channel region, by less than 10 nm; and
an insulating layer on the gate electrode, the insulating layer extending between the sidewalls of the gate electrode and sidewalls of the trench and having a bottommost surface contacting respective topmost surfaces of the gate dielectric and the conductive work function layer.
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