US 12,136,571 B2
Methods for fabricating FinFETs having different fin numbers and corresponding FinFETs thereof
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,122.
Application 17/366,465 is a division of application No. 16/395,552, filed on Apr. 26, 2019, granted, now 11,056,394, issued on Jul. 6, 2021.
Application 18/361,122 is a continuation of application No. 17/366,465, filed on Jul. 2, 2021, granted, now 11,764,112.
Claims priority of provisional application 62/691,416, filed on Jun. 28, 2018.
Prior Publication US 2023/0369122 A1, Nov. 16, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/31111 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a dummy patterning layer over a semiconductor layer, wherein:
the dummy patterning layer includes a first dummy pattern that extends lengthwise along a first direction in a first type device region,
the dummy patterning layer includes a second dummy pattern that extends lengthwise along the first direction in a second type device region, wherein the first type device region is adjacent to the second type device region, and
the first dummy pattern and the second dummy pattern each have a first portion having a first width and a second portion having a second width, wherein the first width and the second width are along a second direction that is different than the first direction and the second width is greater than the first width;
forming a patterning layer over the semiconductor layer by:
depositing a material layer over the dummy patterning layer and the semiconductor layer, wherein a composition of the material layer is different than a composition of the dummy patterning layer,
etching the material layer to form first material layers along first sidewalls of the first dummy pattern and second material layers along second sidewalls of the second dummy pattern, and
removing the dummy patterning layer;
etching the semiconductor layer using the patterning layer as an etch mask to form a first semiconductor fin, a second semiconductor fin, a third semiconductor fin, and a fourth semiconductor fin extending lengthwise in the first direction, wherein the first semiconductor fin and the second semiconductor fin are in the first type device region, and the third semiconductor fin and the fourth semiconductor fin are in the second type device region; and
performing a patterning and etching process to partially remove a dummy fin region of the second semiconductor fin and a dummy fin region of the third semiconductor fin.