US 12,136,570 B2
Graphene layer for low resistance contacts and damascene interconnects
Mrunal Abhijith Khaderbad, Hsinchu (TW); Wei-Yen Woon, Hsinchu (TW); Cheng-Ming Lin, Kaohsiung (TW); Han-Yu Lin, Nantou (TW); Szu-Hua Chen, Hsinchu (TW); Jhih-Rong Huang, Zhubei (TW); and Tzer-Min Shen, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 14, 2021, as Appl. No. 17/550,670.
Claims priority of provisional application 63/157,517, filed on Mar. 5, 2021.
Prior Publication US 2022/0285221 A1, Sep. 8, 2022
Int. Cl. H01L 21/8234 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/486 (2013.01); H01L 21/76871 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor device, comprising:
forming a fin structure with an epitaxial layer;
forming a catalyst layer in an opening that exposes a top surface of the epitaxial layer;
forming a graphene film at an interface between the catalyst layer and the epitaxial layer; and
forming a metal plug on the graphene film to fill the opening.