US 12,136,565 B2
Semiconductor device package and manufacturing method thereof
Michael G. Kelly, Queen Creek, AZ (US); Ronald Patrick Huemoeller, Gilbert, AZ (US); Won Chul Do, Bucheon-si (KR); and David Jon Hiner, Chandler, AZ (US)
Assigned to AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD., Singapore (SG)
Filed by Amkor Technology Singapore Holding Pte. Ltd., Singapore (SG)
Filed on Aug. 19, 2022, as Appl. No. 17/891,341.
Application 17/891,341 is a continuation of application No. 16/925,546, filed on Jul. 10, 2020, granted, now 11,424,155.
Application 16/925,546 is a continuation of application No. 16/404,264, filed on May 6, 2019, granted, now 10,714,378, issued on Jul. 14, 2020.
Application 16/404,264 is a continuation of application No. 15/973,329, filed on May 7, 2018, granted, now 10,283,400, issued on May 7, 2019.
Application 15/973,329 is a continuation of application No. 14/698,634, filed on Apr. 28, 2015, granted, now 9,966,300, issued on May 8, 2018.
Application 14/698,634 is a continuation of application No. 13/678,058, filed on Nov. 15, 2012, granted, now 9,136,159, issued on Sep. 15, 2015.
Application 14/698,634 is a continuation of application No. 13/678,046, filed on Nov. 15, 2012, granted, now 9,040,349, issued on May 26, 2015.
Prior Publication US 2023/0040553 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/683 (2006.01); H01L 21/48 (2006.01); H01L 21/762 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 23/544 (2006.01)
CPC H01L 21/76251 (2013.01) [H01L 21/486 (2013.01); H01L 21/6838 (2013.01); H01L 23/147 (2013.01); H01L 23/3107 (2013.01); H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/5386 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 24/95 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/544 (2013.01); H01L 24/13 (2013.01); H01L 2221/68322 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/81001 (2013.01); H01L 2224/81011 (2013.01); H01L 2224/81024 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83101 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/83855 (2013.01); H01L 2224/92125 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/16152 (2013.01); H01L 2924/1616 (2013.01); H01L 2924/19105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
an interposer comprising an interposer top side and an interposer bottom side;
a first device die comprising a first device die top side and a first device die bottom side, wherein the first device die bottom side is coupled to the interposer top side;
a second device die comprising a second device die top side and a second device die bottom side, wherein the second device die bottom side is coupled to the interposer top side; and
a third device die comprising a third device die top side and a third device die bottom side, wherein the third device die bottom side is coupled to the second device die top side.