CPC H01L 21/67288 (2013.01) [G03F 7/0002 (2013.01); H01L 22/12 (2013.01)] | 26 Claims |
1. An apparatus comprising:
a wafer holder to hold one or more test wafers, each having an imprintable field; and
a generator to generate a set of test drop patterns comprising:
a storage device storing a database that contains input parameters of a drop pattern generation (DPG) process for a template;
an input/output (I/O) interface circuit to interface with a user;
a processor; and
a memory storing instructions that, when executed by the processor, cause the processor to perform operations comprising:
receiving a guide command from the user via the I/O interface circuit to guide the DPG process,
retrieving at least one of the input parameters from the database prior to an inspection of imprinted fields for defects;
generating a base drop pattern (BDP) based on the at least one of the input parameters,
estimating a segment required compensation volume (RCV) of edge segments near edges of the imprint field,
generating edge drop arrangements at the edge segments based on the estimated segment RCV and the guide command, and
generating a drop pattern based on the BDP and the edge drop arrangements as one of the drop patterns in the set prior to the inspection of imprinted fields for defects, wherein each drop pattern in the set has different edge arrangements, and
wherein the set of drop patterns is deposited onto the one or more test wafers, the fields are imprinted, the imprinted fields are inspected, and an optimal drop pattern is determined based on the inspection of the imprinted fields for defects.
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