US 12,136,551 B2
Method for forming FinFET super well
Yong Li, Shanghai (CN)
Assigned to Shanghai Huali Integrated Circuit Corporation, Shanghai (CN)
Filed by SHANGHAI HUALI INTEGRATED CIRCUIT CORPORATION, Shanghai (CN)
Filed on Sep. 30, 2021, as Appl. No. 17/491,090.
Claims priority of application No. 202110597507.X (CN), filed on May 31, 2021.
Prior Publication US 2022/0384193 A1, Dec. 1, 2022
Int. Cl. H01L 21/265 (2006.01); H01L 21/308 (2006.01)
CPC H01L 21/26513 (2013.01) [H01L 21/3086 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for forming a FinFET super well, comprising steps of:
step 1: providing a silicon substrate having a deep N-well, disposing a first oxide layer on the silicon substrate;
step 2: forming a well region in the silicon substrate above the deep N-well;
step 3: forming a hard mask layer on the first oxide layer, and forming a second oxide layer on the hard mask layer;
step 4: patterning the second oxide layer and the hard mask layer to form a plurality of structures until an upper surface of the first oxide layer is exposed after the patterning, wherein the plurality of structures is spaced from each other;
step 5: etching away the second oxide layer above the hard mask layer, the first oxide layer, and the silicon substrate along the plurality of structures until a first height of each of the plurality of structures is reached, wherein the hard mask layer, the first oxide layer, and the silicon substrate at both sides of the plurality of structures form a plurality of fin structures;
step 6: performing a first ion implantation to form a first ion implantation layer at both sides of a root of each of the plurality of fin structures at the first height, wherein the first ion implantation adjusts a threshold voltage;
step 7: etching the silicon substrate along sidewalls of each of the plurality of fin structures until a second height is reached;
step 8: performing a second ion implantation to form a second ion implantation layer at the both sides of the root of each of the plurality of fin structures at the second height;
step 9: etching the silicon substrate along the sidewalls of the plurality of fin structures until a third height is reached;
step 10: performing annealing treatment, wherein the first and the second ion implantation layers in the plurality of fin structures respectively diffuse laterally into full width regions of each of the plurality of fin structures, as well as diffuse longitudinally into the well region and the deep N-well, and an upper surface of the silicon substrate; and
step 11: disposing a third oxide layer by means of FCVD, wherein the third oxide layer fills a region between two adjacent ones of the plurality of fin structures; and
step 12: etching the third oxide layer until a side of the second ion implantation layer in one of the plurality of fin structures is exposed.