	US 12,136,523 B2
	Multilayer capacitor and board having the same mounted thereon
Hwi Dae Kim, Suwon-si (KR); Ji Hong Jo, Suwon-si (KR); Woo Chul Shin, Suwon-si (KR); Chan Yoon, Suwon-si (KR); and Sang Soo Park, Suwon-si (KR)
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRO-MECHANICS CO., LTD., Suwon-si (KR)
Filed on Oct. 26, 2022, as Appl. No. 17/973,727.
Application 17/973,727 is a continuation of application No. 16/774,569, filed on Jan. 28, 2020, granted, now 11,515,094.
Claims priority of application No. 10-2019-0086597 (KR), filed on Jul. 17, 2019.
Prior Publication US 2023/0061474 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01G 4/30 (2006.01); H01G 2/02 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01)

CPC H01G 4/30 (2013.01) [H01G 2/02 (2013.01); H01G 4/012 (2013.01); H01G 4/1209 (2013.01)]

21 Claims

1. A multilayer capacitor comprising:

a capacitor body including a dielectric layer and first and second internal electrodes; and

first and second external electrodes disposed on both ends of the capacitor body and connected to exposed first ends of the first and second internal electrodes, respectively, in a length direction,

wherein A/B satisfies 0.01<A/B<1.0, in which A is an average thickness of the dielectric layer and B is an average length in μm of margins of the capacitor body in the length direction, the margins being portions of the dielectric layer from respective second ends of the first and second internal electrodes, opposite to the exposed first ends, to adjacent side surfaces of the capacitor body, respectively, in the length direction, and

wherein A is 0.4 μm or less.