CPC G11C 7/24 (2013.01) [G06F 21/44 (2013.01); H04L 9/3278 (2013.01)] | 20 Claims |
1. A memory device, comprising:
an array of memory cells;
a physically unclonable function (PUF) circuit in the memory device to generate PUF codes;
a deterministic random bit generator (DRBG) to generate a sequence of at least pseudo random numbers;
a data path directly connecting the array of memory cells and the DRBG, the data path including (i) a first path, having first and second endpoints, the first endpoint connecting a first circuit comprising a first set of memory cells at a first location in the array of memory cells storing a PUF code, and the second endpoint connecting to the DRBG in the memory device, and (ii) a second path, having first and second endpoints, the first endpoint connecting the DRBG, and the second endpoint connecting to a second set of memory cells at a second location in the array of memory cells for storing keys.
|