US 12,136,468 B2
Calibration methods and structures for partitioned memory architecture with single resistor or dual resistor memory elements
Venkatesh P. Gopinath, Fremont, CA (US); and Pirooz Parvarandeh, Los Altos Hills, CA (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Oct. 11, 2022, as Appl. No. 18/045,529.
Prior Publication US 2024/0119974 A1, Apr. 11, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 13/00 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1012 (2013.01); G11C 7/12 (2013.01); G11C 13/0069 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
an array of memory banks arranged in rows and columns, wherein each memory bank comprises:
input nodes;
at least one bitline;
memory elements, wherein each memory element comprises at least one programmable resistor connected between a corresponding input node and the at least one bitline; and
at least one feedback buffer circuit connected to the at least one bitline, and
wherein each row of the memory banks in the array comprises an initial memory bank comprising:
amplifiers connected in series between the input nodes and the memory elements, respectively;
track-and-hold devices;
a calibration supply line; and
multiplexors, wherein each multiplexor has an output connected to an amplifier and at least a first input connected to a track-and-hold device and a second input connected to the calibration supply line.