CPC G11C 7/04 (2013.01) [G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); H03K 19/21 (2013.01); H03L 7/0995 (2013.01)] | 17 Claims |
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
receiving a first oscillator count value at a first time and a second oscillator count value at a second time, wherein the first time precedes the second time;
comparing the first oscillator count value to the second oscillator count value; and
responsive to determining that a difference between the first oscillator count value and the second oscillator count value satisfies a criterion, adjusting a propagation delay for performing write operations on the memory device.
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