US 12,136,461 B2
Memory programming operation comprising preprogramming memory cells
Che-Ping Chen, Taipei (TW); and Ya-Jui Lee, Taichung (TW)
Assigned to Macronix International Co., Ltd., Hsinchu (TW)
Filed by Macronix International Co., Ltd., Hsinchu (TW)
Filed on Aug. 5, 2021, as Appl. No. 17/394,850.
Prior Publication US 2023/0041949 A1, Feb. 9, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3409 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method performed by a memory controller, the method comprising:
receiving a command to program information to a memory storage array controlled by the memory controller;
determining a plurality of target memory states to store the information, the plurality of target memory states including a first memory state and a second memory state;
determining a plurality of target threshold voltage levels corresponding to the plurality of target memory states, the plurality of target threshold voltage levels including a first target voltage level corresponding to the first memory state and a second target voltage level corresponding to the second memory state, the second target voltage level being higher than the first target voltage level;
determining, based at least on the plurality of target memory states, one or more program pulses for a pre-program cycle, the one or more program pulses including a combined program pulse for pre-programming the first memory state and the second memory state;
computing, based at least on the plurality of target threshold voltage levels, voltage levels for the one or more program pulses, the computing comprising determining a first voltage level for the combined program pulse to be within a specified range of the first target voltage level that is less than the first target voltage level such that a threshold voltage of the selected memory location upon completion of the preprogramming is less than the first target voltage level and within the specified range of the first target voltage level;
selecting a memory location in the memory storage array to program the information;
pre-programming the selected memory location by applying the one or more program pulses at respective voltage levels, including applying the combined program pulse at the first voltage level to pre-program the memory location for the first memory state and the second memory state, the one or more program pulses applied without program verify operations; and
following the pre-programming, programming the information to the selected memory location.