US 12,136,460 B2
Floating data line circuit and method
Manish Arora, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); Hung-Jen Liao, Hsinchu (TW); Nikhil Puri, Hsinchu (TW); and Yu-Hao Hsu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,549.
Application 18/362,549 is a continuation of application No. 17/313,404, filed on May 6, 2021, granted, now 11,798,632.
Application 17/313,404 is a continuation of application No. 16/204,268, filed on Nov. 29, 2018, granted, now 11,011,238, issued on May 18, 2021.
Claims priority of provisional application 62/691,599, filed on Jun. 28, 2018.
Prior Publication US 2023/0395160 A1, Dec. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/24 (2006.01); G11C 7/12 (2006.01); G11C 11/00 (2006.01); G11C 16/04 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01)
CPC G11C 16/24 (2013.01) [G11C 7/12 (2013.01); G11C 11/005 (2013.01); G11C 16/0483 (2013.01); H10B 41/20 (2023.02); H10B 41/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory circuit comprising:
first and second memory segments;
first and second write lines coupled to each of the first and second memory segments;
a first write line circuit coupled to the first write line and configured to receive first and second data signals; and
a second write line circuit coupled to the second write line and configured to receive the first and second data signals,
wherein
the memory circuit is configured to:
cause the first and second data signals to have complementary low and high logical states during a write operation to the first or second memory segment, and
cause each of the first and second data signals to have the low logical state during a masked write operation to the first or second memory segment, the first write line circuit is configured to:
output, to the first write line, a first write line signal responsive to the first data signal during the write operation, and
float the first write line during the masked write operation, and the second write line circuit is configured to:
output, to the second write line, a second write line signal responsive to the second data signal during the write operation, and
float the second write line during the masked write operation.