US 12,136,458 B2
Semiconductor memory device
Tomoki Nakagawa, Yokohama Kanagawa (JP); Koji Kato, Yokohama Kanagawa (JP); Shuhei Oketa, Yokohama Kanagawa (JP); and Mai Shimizu, Kamakura Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Aug. 26, 2022, as Appl. No. 17/897,089.
Claims priority of application No. 2022-047799 (JP), filed on Mar. 24, 2022.
Prior Publication US 2023/0307051 A1, Sep. 28, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01)
CPC G11C 16/08 (2013.01) [G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory string including a first select transistor, a plurality of memory cell transistors, and a second select transistor connected in series;
a voltage supply circuit configured to generate a plurality of operation voltages to operate the semiconductor memory device, the operation voltages including a negative voltage;
a plurality of control signal lines connected between the voltage supply circuit and the memory string, the plurality of control signal lines including a word line connected to a gate of one of the memory transistors;
a row decoder including a plurality of transistors provided in the plurality of control signal lines, respectively; and
a control circuit configured to control the transistors of the row decoder and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level, the certain period of time including a first period of time during which a voltage of the word line drops to a negative level.