US 12,136,457 B2
Multinary bit cells for memory devices and network applications and method of manufacturing the same
Katherine H. Chiang, New Taipei (TW); and Chung-Te Lin, Taiwan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/354,565.
Application 18/354,565 is a division of application No. 17/699,253, filed on Mar. 21, 2022, granted, now 11,749,341.
Application 17/699,253 is a division of application No. 16/901,051, filed on Jun. 15, 2020, granted, now 11,282,572, issued on Mar. 22, 2022.
Prior Publication US 2023/0360698 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/24 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G11C 11/56 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 49/02 (2006.01); H10B 99/00 (2023.01)
CPC G11C 11/565 (2013.01) [G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/124 (2013.01); H01L 27/1255 (2013.01); H01L 27/1259 (2013.01); H01L 28/60 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H10B 99/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a multinary memory cell, comprising:
depositing N layer stack units over a substrate, wherein N is an integer greater than 1, and each layer stack unit selected from the N layer stack units comprises an isolation dielectric layer, a gate electrode layer, a gate dielectric layer, a semiconductor channel layer, a dielectric spacer layer, a capacitor dielectric layer, and a ground electrode layer;
etching trenches through the N layer stack units;
laterally etching patterned portions of each dielectric spacer layer, wherein lateral recesses are formed adjacent to dielectric spacer plates that are remaining portions of the dielectric spacer layers;
depositing a semiconductor material or a conductive material in the lateral recesses, where a composite layer including a dielectric spacer plate, a source region, and a drain region is formed on each of the semiconductor channel layers to provide a respective transistor; and
forming a bit line on each set of drain regions that overlie or underlie one another, wherein a parallel connection of N sub-bit units is formed, wherein each of the N sub-bit units comprises a series connection of a respective transistor and a respective capacitor including the source region of the respective transistor, a patterned portion of a respective capacitor dielectric layer, and a patterned portion of a respective ground electrode layer.