US 12,136,454 B2
Memory device having a comparator circuit
Jaspal Singh Shah, Ottawa (CA); and Atul Katoch, Kanata (CA)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/814,673.
Application 17/814,673 is a continuation of application No. 17/085,420, filed on Oct. 30, 2020, granted, now 11,398,271.
Claims priority of provisional application 62/954,903, filed on Dec. 30, 2019.
Prior Publication US 2022/0358999 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/418 (2006.01)
CPC G11C 11/418 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method of operating a memory device, the method comprising:
generating a first precompute signal and a second precompute signal, wherein generating the first precompute signal and the second precompute signal comprises generating the first precompute signal and the second precompute signal from a previous memory output signal and a Compare input and Control (CIC) signal before a cell data signal;
receiving the cell data signal from a memory cell in a respective column of memory cells; and
selecting, based on the cell data signal, one of the first precompute signal and the second precompute signal to output from the comparator circuitry as a memory output signal for the memory array.