US 12,136,453 B2
Systems, methods and media of optimization of temporary read errors in 3D NAND memory devices
Jianquan Jia, Hubei (CN); Kaikai You, Hubei (CN); Xinlei Jia, Hubei (CN); Wen Zhou, Hubei (CN); Kun Yang, Hubei (CN); Jiayin Han, Hubei (CN); Pan Xu, Hubei (CN); Zhe Luo, Hubei (CN); Da Li, Hubei (CN); and Lei Jin, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Aug. 2, 2022, as Appl. No. 17/879,593.
Prior Publication US 2024/0046980 A1, Feb. 8, 2024
Int. Cl. G11C 16/00 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4096 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells arranged as an array of NAND memory strings;
a plurality of word lines coupled to the memory cells; and
a controller configured to:
determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and
in response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation, wherein the first read operation comprises:
ramping up selected word lines from a ground voltage to a read pass voltage; and
after a first time period, ramping down the selected word lines from the read pass voltage to the ground voltage.