US 12,136,452 B2
Method and apparatus for calibrating write timing in a memory system
Thomas J. Giovannini, San Jose, CA (US); Alok Gupta, Fremont, CA (US); Ian Shaeffer, Los Gatos, CA (US); and Steven C. Woo, Saratoga, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 14, 2023, as Appl. No. 18/209,976.
Application 18/209,976 is a continuation of application No. 17/852,286, filed on Jun. 28, 2022, granted, now 11,682,448.
Application 17/852,286 is a continuation of application No. 16/823,116, filed on Mar. 18, 2020, granted, now 11,404,103, issued on Aug. 2, 2022.
Application 16/823,116 is a continuation of application No. 16/408,368, filed on May 9, 2019, granted, now 10,607,685, issued on Mar. 31, 2020.
Application 16/408,368 is a continuation of application No. 15/872,848, filed on Jan. 16, 2018, granted, now 10,304,517, issued on May 28, 2019.
Application 15/872,848 is a continuation of application No. 15/406,373, filed on Jan. 13, 2017, granted, now 9,881,662, issued on Jan. 30, 2018.
Application 15/406,373 is a continuation of application No. 14/931,513, filed on Nov. 3, 2015, granted, now 9,552,865, issued on Jan. 24, 2017.
Application 14/931,513 is a continuation of application No. 14/714,722, filed on May 18, 2015, granted, now 9,177,632, issued on Nov. 3, 2015.
Application 14/714,722 is a continuation of application No. 12/049,928, filed on Mar. 17, 2008, granted, now 9,263,103, issued on Feb. 16, 2016.
Claims priority of provisional application 61/016,317, filed on Dec. 21, 2007.
Prior Publication US 2023/0410880 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 1/08 (2006.01); G06F 3/06 (2006.01); G06F 5/06 (2006.01); G06F 12/06 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 11/4076 (2006.01); G11C 11/409 (2006.01); G11C 29/02 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4076 (2013.01) [G06F 1/08 (2013.01); G06F 3/0629 (2013.01); G06F 3/0634 (2013.01); G06F 5/06 (2013.01); G06F 12/0646 (2013.01); G06F 13/1689 (2013.01); G11C 7/1078 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 11/409 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 11/4096 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a clock transmitter to transmit a clock signal;
an interface to transmit to a memory device, during a write leveling calibration mode, a data-strobe signal and a command signal that marks a specific clock cycle in the clock signal; and
a receiver to receive a feedback signal from the memory device during the write leveling calibration mode, the feedback signal generated by the memory device using the command signal and the received data-strobe signal.