US 12,136,448 B2
Memory accessing with auto-precharge
Shivam Swami, Folsom, CA (US); Sean S. Eilert, Penryn, CA (US); and Ameen D. Akel, Rancho Cordova, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 22, 2022, as Appl. No. 17/846,751.
Application 17/846,751 is a continuation of application No. 16/719,907, filed on Dec. 18, 2019, granted, now 11,373,695.
Prior Publication US 2022/0392509 A1, Dec. 8, 2022
Int. Cl. G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 11/22 (2006.01)
CPC G11C 11/2259 (2013.01) [G11C 7/08 (2013.01); G11C 7/10 (2013.01); G11C 8/08 (2013.01); G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 11/2293 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, at a memory device, a first command to transition, during a duration in which at least a portion of a plurality of memory cells is deactivated, the memory device from a first state associated with respective access lines of the plurality of memory cells being precharged to a second state associated with a plurality of latches storing respective logic states of the plurality of memory cells;
receiving, at the memory device, an access command for the plurality of memory cells;
transmitting the respective logic states stored in the plurality of latches while a word line associated with the plurality of memory cells is deactivated; and
receiving, at the memory device, a second command to transition the memory device from the second state to a third state associated with the plurality of latches storing the respective logic states and writing a default logic state to the plurality of memory cells.