US 12,136,385 B2
Pixel and display apparatus digitally controlling reset of memory
Ji Han Kim, Seoul (KR); Sung Ho Hwang, Seoul (KR); Ji Haeng Lee, Seoul (KR); Dae Young Jung, Seoul (KR); and Jong Gu Jeon, Seoul (KR)
Assigned to SAPIEN Semiconductors Inc., Gyeonggi-do (KR)
Filed by Sapien Semiconductors Inc., Seoul (KR)
Filed on Jul. 14, 2023, as Appl. No. 18/352,590.
Claims priority of application No. 10-2022-0101249 (KR), filed on Aug. 12, 2022.
Prior Publication US 2024/0054944 A1, Feb. 15, 2024
Int. Cl. G09G 3/32 (2016.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0857 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0278 (2013.01); G09G 2310/061 (2013.01); G09G 2330/021 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A pixel driving circuit comprising:
a memory unit including a data memory and a register, the memory unit stored data related to driving of a luminous element;
a driver supplying electrical power to the luminous element based on the data stored in the memory unit; and
a reset unit controlling reset of the memory unit, wherein
the reset unit generates a first reset signal for controlling reset of the data memory and a second reset signal for controlling reset of the register,
the memory unit stores the data by using a first signal as a clock signal, and
the reset unit generates the first reset signal and the second reset signal by using a second signal as a clock signal.