US 12,136,378 B2
Shift register unit and driving method thereof, gate drive circuit and display device
Weixing Liu, Beijing (CN); Jintao Peng, Beijing (CN); Jiao Li, Beijing (CN); Chunfang Zhang, Beijing (CN); and Xinxing Wang, Beijing (CN)
Assigned to BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/022,479
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Mar. 14, 2022, PCT No. PCT/CN2022/080769
§ 371(c)(1), (2) Date Feb. 21, 2023,
PCT Pub. No. WO2023/173259, PCT Pub. Date Sep. 21, 2023.
Prior Publication US 2024/0265843 A1, Aug. 8, 2024
Int. Cl. G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01)
CPC G09G 3/2092 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0232 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01); G11C 19/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
a first input circuit, connected to a first control terminal, a turn-on signal terminal, a first node and a second node, and configured to control a potential at the first node and a potential at the second node in response to a first control signal provided by the first control terminal and a turn-on signal provided by the turn-on signal terminal;
a second input circuit, connected to a first power supply terminal, the first node and a third node, and configured to control a potential at the third node in response to the potential at the first node and a first power supply signal provided by the first power supply terminal;
an output control circuit, connected to the first node, the second node, the third node, a second control terminal and a fourth node, and configured to control a potential at the fourth node in response to the potential at the first node, the potential at the second node, the potential at the third node and a second control signal provided by the second control terminal; and
an output circuit, connected to the second node, the fourth node, the first power supply terminal, a second power supply terminal, a first output terminal and a second output terminal, and configured to control the first power supply terminal and the second power supply terminal to transmit the first power supply signal and a second power supply signal to the first output terminal and the second output terminal respectively at least within one same time period, in response to the potential at the second node and the potential at the fourth node.