US 12,136,373 B2
Pixel circuit and display device having the same
Sunho Kim, Seongnam-si (KR); Yoomin Ko, Suwon-si (KR); Juchan Park, Seoul (KR); and Pilsuk Lee, Suwon-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by Samsung Display Co., LTD., Yongin-si (KR)
Filed on Mar. 9, 2023, as Appl. No. 18/119,502.
Claims priority of application No. 10-2022-0053018 (KR), filed on Apr. 28, 2022.
Prior Publication US 2023/0351935 A1, Nov. 2, 2023
Int. Cl. G09G 3/20 (2006.01)
CPC G09G 3/20 (2013.01) [G09G 3/2096 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/08 (2013.01); G09G 2320/045 (2013.01); G09G 2330/021 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A pixel circuit comprising:
a first transistor including a control electrode electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node;
a second transistor including a control electrode that receives a write gate signal generated based on clock signals having a duration of M horizontal time, M being a positive integer greater than or equal to 2, a first electrode that receives a data voltage, and a second electrode electrically connected to the second node;
a third transistor including a control electrode that receives a compensation gate signal generated based on a first next write gate signal applied after the write gate signal is applied, a first electrode electrically connected to the third node, and a second electrode electrically connected to the first node;
a first capacitor including a first electrode that receives a first power voltage and a second electrode electrically connected to the first node;
a fourth transistor including a control electrode that receives an initialization gate signal generated based on a previous write gate signal applied before the write gate signal is applied, a first electrode that receives a first initialization voltage, and a second electrode electrically connected to the first node;
a fifth transistor including a control electrode that receives an emission signal, a first electrode that receives the first power voltage, and a second electrode electrically connected to the second node;
a sixth transistor including a control electrode that receives the emission signal, a first electrode electrically connected to the third node, and a second electrode electrically connected to a fourth node; and
a light emitting element including a first electrode electrically connected to the fourth node and a second electrode that receives a second power voltage,
wherein the second transistor is a p-type transistor, and the third transistor and the fourth transistor are n-type transistors, and
wherein the initialization gate signal is generated by inverting the previous write gate signal, and the compensation gate signal is generated by inverting the first next write gate signal.