CPC G09G 3/20 (2013.01) [G09G 2310/0267 (2013.01)] | 20 Claims |
1. A control circuit of a display panel, wherein the control circuit is configured to receive a first clock signal, a first level signal and a second level signal, phase-shift the first clock signal to obtain a second clock signal according to the first level signal and the second level signal, and output the second clock signal to a gate drive circuit; wherein the second clock signal comprises a third level signal and a fourth level signal, the third level signal and the fourth level signal are at different levels;
the control circuit comprises: a first switch unit and a second switch unit connected to the first switch unit;
the first switch unit is configured to receive the first clock signal, the first level signal and the second level signal, and output the third level signal to the gate drive circuit based on the first clock signal, the first level signal and the second level signal; and
the second switch unit is configured to receive the first clock signal, the first level signal and the second level signal, and output the fourth level signal to the gate drive circuit according to the first clock signal, the first level signal and the second level signal.
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