US 12,136,029 B2
Integrated circuit chip apparatus
Shaoli Liu, Beijing (CN); Xinkai Song, Beijing (CN); Bingrui Wang, Beijing (CN); Yao Zhang, Beijing (CN); and Shuai Hu, Beijing (CN)
Assigned to Cambricon Technologies Corporation Limited, Beijing (CN)
Filed by Cambricon Technologies Corporation Limited, Beijing (CN)
Filed on Dec. 20, 2022, as Appl. No. 18/085,332.
Application 18/085,332 is a continuation of application No. 17/010,761, filed on Sep. 2, 2020, granted, now 11,562,219.
Application 17/010,761 is a continuation of application No. 16/721,875, filed on Dec. 19, 2019, granted, now 11,562,216.
Application 16/721,875 is a continuation of application No. PCT/CN2019/073453, filed on Jan. 28, 2019.
Claims priority of application No. 201711343642.1 (CN), filed on Dec. 14, 2017; application No. 201711346333.X (CN), filed on Dec. 14, 2017; application No. 201711347310.0 (CN), filed on Dec. 14, 2017; application No. 201711347406.7 (CN), filed on Dec. 14, 2017; application No. 201711347407.1 (CN), filed on Dec. 14, 2017; application No. 201711347408.6 (CN), filed on Dec. 14, 2017; and application No. 201711347767.1 (CN), filed on Dec. 14, 2017.
Prior Publication US 2023/0121164 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/063 (2023.01); G06F 7/483 (2006.01); G06F 7/544 (2006.01); G06F 17/15 (2006.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/06 (2006.01); G06N 3/08 (2023.01); H01L 25/065 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/483 (2013.01); G06F 7/5443 (2013.01); G06F 17/153 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/06 (2013.01); G06N 3/08 (2013.01); H01L 25/065 (2013.01); G06F 2207/4824 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit chip apparatus, comprising: a main processing circuit and a plurality of basic processing circuits
wherein the main processing circuit is configured to:
receive an input data block, a weight data block, and a multiplication instruction;
designate the input data block as a distribution data block and the weight data block as a broadcasting data block according to the multiplication instruction;
partition the distribution data block to obtain a plurality of basic data blocks;
distribute the plurality of basic data blocks respectively to at least one of the plurality of basic processing circuits; and
broadcast the entire broadcasting data block to each of the plurality of basic processing circuits,
wherein the at least one of the plurality of basic processing circuits is configured to perform computations on the same broadcasting data block and the respective received basic data blocks to obtain computation results, and transfer the computation results to the main processing circuit,
wherein the main processing circuit is configured to process the computation results to obtain an instruction result of the multiplication instruction.