US 12,136,028 B2
Methods and systems of operating a neural circuit in a non-volatile memory based neural-array
Vishal Sarin, Santa Clara, CA (US)
Filed by Vishal Sarin, Santa Clara, CA (US)
Filed on Jun. 25, 2019, as Appl. No. 16/452,308.
Claims priority of provisional application 62/803,562, filed on Feb. 10, 2019.
Claims priority of provisional application 62/773,773, filed on Nov. 30, 2018.
Claims priority of provisional application 62/721,116, filed on Aug. 22, 2018.
Claims priority of provisional application 62/689,839, filed on Jun. 26, 2018.
Prior Publication US 2020/0160165 A1, May 21, 2020
Int. Cl. G06N 3/063 (2023.01); G06F 7/499 (2006.01); G06F 17/16 (2006.01); G06N 3/04 (2023.01); G06N 3/049 (2023.01); G06N 3/065 (2023.01); G06N 3/082 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 7/49942 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/049 (2013.01); G06N 3/065 (2023.01); G06N 3/082 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A method of a neuron circuit comprising:
providing a plurality of 2N−1 single-level-cell (SLC) non-volatile memory (NVM) cells for each synapse (Yi) connected to a bit line forming a neuron, where N is a number of bits in the weight vector or synapse (Yi);
providing an input vector (Xi) for each synapse (Yi) wherein each input vector is translated into an equivalent electrical signal;
providing the electrical signal to each synapse sub-circuit;
providing a set of weight vectors or synapse (Yi), wherein each weight vector is translated into an equivalent threshold voltage level or resistance level to be stored in one of the plurality of SLC non-volatile memory cells assigned to each synapse (Yi);
providing for 2N possible threshold voltage levels or resistance levels in the 2N−1 non-volatile memory cells of each synapse, wherein each non-volatile memory cell is configured to store one of the two or more possible threshold voltage levels or resistance levels;
converting a N digital bits of the weight vector or synapse (Yi) into equivalent threshold voltage level or resistance level and store the appropriate cell corresponding to that threshold voltage level or resistance level in one of the plurality of SLC cells assigned to the weight vector or synapse (Yi); and
turning off all remaining 2N−1 non-volatile memory cells of the respective synapse (Yi), and
wherein a neural cell comprises a flash-cell system, wherein an equation for a neural cell comprises Eqneuron=Σ(xi*yi)+b, where, xj is the set of input vectors, yi is parameter which is related to a threshold voltage of individual flash cells, and b is a bias variable.