	US 12,136,019 B2
	System and method for latency-aware mapping of quantum circuits to quantum chips
Ali Javadiabhari, Sleepy Hollow, NY (US); Scott Douglas Lekuch, New York, NY (US); and Ken Inoue, Elmsford, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Oct. 21, 2022, as Appl. No. 18/048,522.
Application 18/048,522 is a continuation of application No. 16/446,426, filed on Jun. 19, 2019, granted, now 11,537,925.
Prior Publication US 2023/0169379 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 10/00 (2022.01); B82Y 10/00 (2011.01); H03M 1/66 (2006.01)

CPC G06N 10/00 (2019.01) [B82Y 10/00 (2013.01); H03M 1/662 (2013.01)]

20 Claims

1. A quantum computing system, comprising:

a quantum processor comprising a plurality of qubits;

a classical computer that generates a quantum circuit by:

selecting at least two qubits of the plurality of qubits to be controlled, via analog conversion units, by inputs from the classical computer that are mapped to corresponding classical bits of the classical computer, wherein the at least two qubits are selected so that the quantum circuit has a latency less than or equal to a threshold latency that is less than or equal to a coherence time of the quantum circuit; and

generating the quantum circuit including the at least two qubits and the corresponding classical bits.