CPC G06K 19/07747 (2013.01) [G06K 19/07779 (2013.01)] | 16 Claims |
1. A smart IC substrate comprising:
a substrate including one surface and an other surface;
a circuit pattern and a connection circuit pattern disposed on the one surface; and
a coil pattern disposed on the other surface,
wherein a chip mounting region is formed on the other surface,
wherein the coil pattern is electrically connected to a first terminal and a second terminal,
wherein the substrate includes a first region disposed inside the coil pattern and a second region disposed outside the coil pattern,
wherein the first terminal is disposed in the first region,
wherein the second terminal is disposed in the second region,
wherein the second terminal and the connection circuit pattern include an overlapping region in which they overlap each other in a vertical direction,
wherein a first via is formed in the first region corresponding to the circuit pattern of the substrate,
wherein a second via is formed in the second region of the substrate and is formed in the overlapping region,
wherein a third via is formed in the first region corresponding to the connection circuit pattern of the substrate,
wherein a connection member is disposed to fill inside the second via, and
wherein the second terminal is connected to the connection circuit pattern by the connection member.
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