US 12,136,000 B2
Programming flow for multi-processor system
Michael L. Purnell, Scotts Valley, CA (US); Geoffrey N. Ellis, Santa Cruz, CA (US); and Teng-I Wang, Yorba Linda, CA (US)
Assigned to Coherent Logix, Incorporated, Austin, TX (US)
Filed by Coherent Logix, Incorporated, Austin, TX (US)
Filed on Apr. 20, 2023, as Appl. No. 18/136,976.
Application 18/136,976 is a continuation of application No. 16/177,680, filed on Nov. 1, 2018, granted, now 11,755,382.
Claims priority of provisional application 62/581,525, filed on Nov. 3, 2017.
Prior Publication US 2023/0359509 A1, Nov. 9, 2023
Int. Cl. G06F 9/50 (2006.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 13/28 (2006.01)
CPC G06F 9/5077 (2013.01) [G06F 8/443 (2013.01); G06F 9/3877 (2013.01); G06F 9/5038 (2013.01); G06F 9/5066 (2013.01); G06F 13/28 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
by a multi-processor array comprising a plurality of processors interspersed among a plurality of memories;
performing a front-end compilation using application source code to generate a plurality of intermediate representations and connectivity information, wherein a particular intermediate representation of the plurality of intermediate representations corresponds to a particular task of a plurality of tasks, wherein the connectivity information includes a plurality of connections, and wherein a particular connection specifies a communication between a first task of the plurality of tasks and a second task of the plurality of tasks;
mapping logical objects included in the application source code to physical resources included in the multi-processor array using the plurality of intermediate representations and the connectivity information to generate a resource map, wherein mapping the logical objects to the physical resources is constrained by one or more of a plurality of constraints;
selecting a respective implementation for each connection in the plurality of connections;
performing a first optimization operation using the plurality of intermediate representations to generate a plurality of optimized intermediate representations, wherein the first optimization operation modifies the mapping of the logical objects to the physical resources to assign multiple tasks to a single processor of the plurality of processors while avoiding one or both of saving and restoring state information;
generating executable code using the plurality of optimized intermediate representations; and
loading the executable code onto the multi-processor array.