US 12,135,993 B2
Hybrid memory in a dynamically power gated hardware accelerator
Paolo Di Febbo, Redwood City, CA (US); Yohan Rajan, Cupertino, CA (US); Chaminda Nalaka Vidanagamachchi, San Jose, CA (US); and Anthony Ghannoum, Santa Clara, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on May 23, 2023, as Appl. No. 18/321,919.
Application 18/321,919 is a continuation of application No. 16/919,930, filed on Jul. 2, 2020, granted, now 11,693,699.
Prior Publication US 2023/0409397 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 9/30 (2018.01)
CPC G06F 9/5016 (2013.01) [G06F 9/3004 (2013.01); G06F 9/5044 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
one or more processor circuits;
a hardware accelerator circuit coupled to the one or more processor circuits, wherein the hardware accelerator circuit is configured to perform operations based on instruction words received from the one or more processor circuits;
a memory coupled to the hardware accelerator circuit, wherein the memory is dedicated to the hardware accelerator circuit, and wherein the memory includes a non-volatile portion reserved for storing data of a first type and a volatile portion reserved for storing data of a second type, wherein the volatile portion is divided into a plurality of sections; and
a power control circuit configured to, during performance of a task specified by a given instruction word provided by one of the one or more processor circuits, cause selected ones of the plurality of sections specified by a power field of the given instruction word to be powered on.