US 12,135,987 B2
Thread scheduling control and memory splitting in a barrel processor
Chris Baronne, Allen, TX (US); Dean E. Walker, Allen, TX (US); and John Amelio, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 20, 2020, as Appl. No. 17/075,096.
Prior Publication US 2022/0121487 A1, Apr. 21, 2022
Int. Cl. G06F 9/48 (2006.01); G06F 9/30 (2018.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 9/3009 (2013.01); G06F 9/30101 (2013.01); G11C 7/1072 (2013.01); G11C 7/22 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a barrel processor, comprising:
thread scheduling circuitry;
wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to:
place a thread to be scheduled in one of two groups by assigning an index to the thread that corresponds to the one of the two groups:
a first group and a second group, wherein the first group is associated with a first processor storage device and has a first set of indexes, and the second group is associated with a second processor storage device and has a second set of indexes; and
wherein threads are selected to be in the first group based on having instructions with alternating reads and writes to the first processor storage device such that two threads in the first group do not have a read and a write to the first processor storage device on a same clock cycle to remove contention between the instructions to access ports to the first processor storage device; and
schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.