decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision floating-point data values from the identified first and second source operands to packed bfloat8 data values using bias terms from the identified source/destination operand and store the packed bfloat8 data values into corresponding data element positions of the identified source/destination operand; and

execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data values from the identified first and second source operands to packed bfloat8 data values using bias terms from the identified source/destination operand and store the packed bfloat8 data values into corresponding data element positions of the identified source/destination operand.