US 12,135,956 B2
Analog adders for multi-bit MAC arrays in reconfigurable analog based neural networks
Seyed Arash Mirhaj, Poway, CA (US); Ankit Srivastava, San Diego, CA (US); and Sameer Wadhwa, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 10, 2021, as Appl. No. 17/197,359.
Prior Publication US 2022/0291900 A1, Sep. 15, 2022
Int. Cl. G06F 7/544 (2006.01); G06G 7/14 (2006.01); G06G 7/16 (2006.01)
CPC G06F 7/5443 (2013.01) [G06G 7/14 (2013.01); G06F 2207/4814 (2013.01); G06G 7/16 (2013.01)] 28 Claims
OG exemplary drawing
 
1. A multi-bit multiplier-accumulator (MAC), comprising an analog adder having a first adder capacitor,
wherein the first adder capacitor is configured to add a plurality of single-bit MAC outputs by:
receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs; and
storing the plurality of single-bit MAC outputs;
wherein the analog adder is configured to output a multi-bit MAC output based on addition of the stored plurality of single-bit MAC outputs, and
wherein the plurality of single-bit MACs are each configured to:
sequentially multiply individual bits of a first multi-bit value and a different single bit of a second multi-bit value, wherein the first multi-bit value and the second multi-bit value are represented by digital voltages; and
accumulate results of the multiplications to generate the plurality of single-bit MAC outputs, wherein the plurality of single-bit MAC outputs are analog voltages.