multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values, wherein the plurality of columns of subproducts comprises a plurality of subproducts and each column of the plurality of columns comprises one or more subproducts of the plurality of subproducts; and

adder circuitry configured to determine a plurality of sums, wherein each sum of the plurality of sums is a sum of one column of the plurality of columns, wherein a first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value associated with the first column, a second value associated with the first column, and a third value associated with a second column of the plurality of columns that differs from the first column, wherein the third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column, and wherein the first portion of the adder circuitry comprises:

ternary adder circuitry configured to add the first portion of the first value, a second portion of the second value, and the third value, wherein the first portion of the first value, the second portion of the second value, and the third value each include a first number of bits;

compressor circuitry communicatively coupled to the ternary adder circuitry, wherein the compressor circuitry is configured to receive a first remaining portion of the first value and a second remaining portion of the second value, wherein the first remaining portion of the first value and the second remaining portion of the second value each include a second number of bits, wherein the second number of bits is greater than the first number of bits; and

binary adder circuitry communicatively coupled to the compressor circuitry, wherein the binary adder circuitry is configured to output a sum of the first remaining portion of the first value and the second remaining portion of the second value.