US 12,135,930 B2
Integrated circuit layout generation method and system
Ke-Ying Su, Taipei (TW); Ke-Wei Su, Zhubei (TW); Keng-Hua Kuo, Hsinchu (TW); and Lester Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/519,405.
Application 18/519,405 is a continuation of application No. 17/031,610, filed on Sep. 24, 2020, granted, now 11,842,135.
Application 17/031,610 is a continuation of application No. 16/294,735, filed on Mar. 6, 2019, granted, now 10,796,059, issued on Oct. 6, 2020.
Claims priority of provisional application 62/646,808, filed on Mar. 22, 2018.
Prior Publication US 2024/0111935 A1, Apr. 4, 2024
Int. Cl. G06F 30/392 (2020.01); G06F 30/20 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/20 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
receiving the IC layout diagram comprising:
an active region;
a gate region extending across the active region from a first active region edge to a second active region edge; and
a gate via positioned at a location along the gate region between the first and second edges;
configuring a delta resistance network comprising the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges; and
performing a simulation based on the delta resistance network.