CPC G06F 30/392 (2020.01) [G06F 30/20 (2020.01)] | 20 Claims |
1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
receiving the IC layout diagram comprising:
an active region;
a gate region extending across the active region from a first active region edge to a second active region edge; and
a gate via positioned at a location along the gate region between the first and second edges;
configuring a delta resistance network comprising the first and second edges, a midpoint between the first and second edges, and resistance values based on the location and first and second edges; and
performing a simulation based on the delta resistance network.
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