US 12,135,901 B2
Joint command dynamic random access memory (DRAM) apparatus and methods
Torsten Partsch, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Appl. No. 17/637,724
Filed by Rambus Inc., San Jose, CA (US)
PCT Filed Aug. 25, 2020, PCT No. PCT/US2020/047850
§ 371(c)(1), (2) Date Feb. 23, 2022,
PCT Pub. No. WO2021/041445, PCT Pub. Date Mar. 4, 2021.
Claims priority of provisional application 62/892,338, filed on Aug. 27, 2019.
Prior Publication US 2022/0283743 A1, Sep. 8, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) dynamic random access memory (DRAM) device, comprising:
memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address; and
a command/address (C/A) interface to receive C/A information defining a joint command, the joint command including information specifying
a first memory access operation with command encoding corresponding to the first memory access operation,
a first bank group address associated with the first memory access operation, and
a second memory access operation to be automatically directed to the first bank group address without command encoding corresponding to the second memory access operation.