US 12,135,887 B2
Sequential data optimized sub-regions in storage devices
David Aaron Palmer, Boise, ID (US); Sean L Manion, Boise, ID (US); Jonathan Scott Parry, Boise, ID (US); Stephen Hanna, Fort Collins, CO (US); Qing Liang, Boise, ID (US); Nadav Grosz, Broomfield, CO (US); Christian M. Gyllenskog, Meridian, ID (US); and Kulachet Tanpairoj, Santa Clara, CA (US)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Sep. 11, 2023, as Appl. No. 18/464,630.
Application 18/464,630 is a continuation of application No. 17/702,217, filed on Mar. 23, 2022, granted, now 11,755,214.
Application 17/702,217 is a continuation of application No. 17/129,087, filed on Dec. 21, 2020, granted, now 11,294,585, issued on Apr. 5, 2022.
Application 17/129,087 is a continuation of application No. 16/237,134, filed on Dec. 31, 2018, granted, now 10,871,907, issued on Dec. 22, 2022.
Prior Publication US 2024/0020033 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/02 (2006.01)
CPC G06F 3/0631 (2013.01) [G06F 3/061 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7204 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A storage system, comprising:
memory; and
a controller configured to perform operations including:
partitioning the memory into a plurality of portions having non-overlapping logical block addressing (LBA) ranges; and
assigning a respective performance level to a respective logical-to-physical (L2P) mapping table entry for each of the plurality of portions of the memory, wherein at least two of the performance levels are different from each other, and wherein the respective L2P mapping table entry comprises a respective granularity.