US 12,135,884 B2
Disaggregated memory server having chassis with a plurality of receptacles accessible configured to convey data with PCIe bus and plurality of memory banks
Thao Nguyen, San Jose, CA (US); Steven White, San Jose, CA (US); and Scott Burns, San Jose, CA (US)
Assigned to TORmem Inc., San Jose, CA (US)
Filed by TORmem Inc., San Jose, CA (US)
Filed on Dec. 21, 2022, as Appl. No. 18/086,488.
Application 18/086,488 is a continuation of application No. 17/743,277, filed on May 12, 2022, granted, now 11,561,697.
Claims priority of provisional application 63/225,258, filed on Jul. 23, 2021.
Claims priority of provisional application 63/187,754, filed on May 12, 2021.
Prior Publication US 2023/0205432 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 13/42 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 3/061 (2013.01); G06F 3/064 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 3/0683 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A server-device, comprising:
a chassis configured to be mounted in a server rack;
a circuit board configured to convey Peripheral Component Interconnect Express (PCIe) bus data between a first connection interface and second connection interface coupled to the circuit board, the circuit board mounted to the chassis and the second connection interface configured to convey PCIe bus data between the circuit board and a PCIe bus of another computing device, the another computing device comprising one or more processors;
a memory module coupled to the circuit board via the first connection interface, the first connection interface configured to convey PCIe bus data between the memory module and the circuit board, the memory module comprising:
a plurality of dual in-line memory module (DIMM) slots configured to receive memory for forming a pool of at least 256 gigabytes of volatile memory; and
a memory controller coupled to the DIMM slots and the first connection interface, the memory controller configured to convey the PCIe bus data between the first connection interface and a portion of the pool of volatile memory accessed by the another computing device as system memory.