| CPC G06F 3/0619 (2013.01) [G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01)] | 14 Claims |
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1. A memory device, comprising:
a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks;
peripheral circuits configured to perform a program operation on a memory block selected from among the plurality of memory blocks and configured to, when a program failure occurs during the program operation, move and store first data stored in a failed sub-block in which the program failure has occurred, among the plurality of sub-blocks, to a replacement block, among the plurality of memory blocks; and
control logic configured to control the peripheral circuits to perform the program operation and generate bad block information from information about the failed sub-block,
wherein each of the plurality of memory blocks comprises a plurality of physical pages corresponding to a plurality of word lines, each of the plurality of sub-blocks comprises one or more of the plurality of physical pages, and the one or more of the plurality of physical pages comprised in each of the plurality of sub-blocks are different from each other, and
wherein the peripheral circuits move and store the first data, stored in the failed sub-block, to the replacement block, and thereafter erase the failed sub-block.
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