US 12,135,882 B2
Memory device and method of operating the same
Chan Hui Jeong, Icheon-si (KR); Hyung Jin Choi, Icheon-si (KR); and Se Chun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 18, 2022, as Appl. No. 17/968,083.
Claims priority of application No. 10-2022-0067421 (KR), filed on Jun. 2, 2022.
Prior Publication US 2023/0393759 A1, Dec. 7, 2023
Int. Cl. G11C 16/08 (2006.01); G06F 3/06 (2006.01); G11C 29/50 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells coupled to a plurality of word lines;
a peripheral circuit configured to perform a word line test operation of determining a weak word line among the plurality of word lines; and
a weak word line determiner configured to control the peripheral circuit such that a result, obtained by comparing a number of first off-cells identified through a first pre-program operation with a number of second off-cells identified through a second pre-program operation, is stored in any one memory block during the word line test operation,
wherein the first pre-program operation is an operation of applying a precharge voltage to a source line coupled in common to the plurality of memory cells and thereafter applying a pre-program voltage to a selected word line among the plurality of word lines, and
wherein the second pre-program operation is an operation of applying a ground voltage to the source line and thereafter applying the pre-program voltage to the selected word line.