US 12,135,878 B2
Programming frequently read data to low latency portions of a solid-state storage array
Yijie Zhao, Milpitas, CA (US); Peter E. Kirkpatrick, Los Altos, CA (US); and Andrew R. Bernat, Mountain View, CA (US)
Assigned to PURE STORAGE, INC., Santa Clara, CA (US)
Filed by PURE STORAGE, INC., Mountain View, CA (US)
Filed on Nov. 24, 2021, as Appl. No. 17/535,116.
Application 17/535,116 is a continuation of application No. 16/255,063, filed on Jan. 23, 2019, granted, now 11,194,473.
Prior Publication US 2022/0083235 A1, Mar. 17, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/0868 (2016.01); G11C 11/408 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0607 (2013.01); G06F 3/0647 (2013.01); G06F 3/0658 (2013.01); G06F 3/0685 (2013.01); G06F 12/0868 (2013.01); G11C 11/4085 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of solid-state storage devices; and
a storage controller operatively coupled to the plurality of solid-state storage devices, the storage controller comprising a processing device, the processing device to:
receive one or more characteristics associated with data stored at a storage array, the one or more characteristics comprising a read count associated with the data;
program a portion of a solid-state memory of a first solid-state drive from a first mode to a second mode based on one or more characteristics associated with the portion of the solid-state memory; and
relocate the data to the portion of the solid-state memory from a second solid-state drive based on an error rate associated with the data, the read count, and a timestamp of a most recent read of the data.