US 12,135,876 B2
Memory systems having controllers embedded in packages of integrated circuit memory
Samir Mittal, Palo Alto, CA (US); Gurpreet Anand, Pleasanton, CA (US); Ying Yu Tai, Mountain View, CA (US); and Cheng Yuan Wu, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 17, 2018, as Appl. No. 16/162,905.
Claims priority of provisional application 62/626,527, filed on Feb. 5, 2018.
Prior Publication US 2019/0243787 A1, Aug. 8, 2019
Int. Cl. G06F 3/06 (2006.01); G06F 9/445 (2018.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G11C 16/20 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0647 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 9/445 (2013.01); G06F 13/1684 (2013.01); G06F 13/4234 (2013.01); G06F 13/4247 (2013.01); G11C 16/20 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A memory component, comprising:
integrated circuit memory dies having a plurality of memory units, each die of the integrated circuit memory dies having at least one memory unit, and the integrated circuit memory dies including a first memory tier having a first access speed, and a second memory tier having a second access speed slower than the first access speed, wherein:
the first memory tier comprises at least one of static random-access memory, dynamic random-access memory, or cross point memory; and
the second memory tier comprises at least one of cross point memory, single level cell flash memory, triple level cell flash memory, or quad-level cell flash memory;
an embedded controller comprising a serial communication interface, the embedded controller being coupled to the first memory tier and to the second memory tier, the embedded controller constructed in a die separated from the integrated circuit memory dies and configured to receive packets via the serial communication interface, wherein the embedded controller is configured to store status information of the integrated circuit memory dies; and
an integrated circuit package that encapsulates the embedded controller and the integrated circuit memory dies;
wherein the embedded controller is configured to at least:
receive a data access stream comprising data access requests, via the serial communication interface, from a serial connection outside of the integrated circuit package;
direct the data access stream to the first memory tier, wherein the first memory tier is used as a cache;
determine a cache hit ratio indicative of:
a number of cache hits comprising a first number of the data access requests that request data stored in the cache of the first memory tier as compared to
a number of cache misses comprising a second number of the data access requests that request data not stored in the cache of the first memory tier;
identify data movements implemented by the embedded controller responsive to the data access requests;
determine, using a trained prediction model comprising a model trained using:
the identified data movements; and
virtual functions configured to identify at least one of (i) an identity of a virtual machine associated with a given data access request, (ii) an identity of an application associated with the given data access request, or (iii) an identity of a user account associated with the given data access request,
predicted data movements to move data between the first memory tier and the second memory tier to increase the cache hit ratio;
implement, continuously and in real time based on new data access requests, the predicted data movements to increase the cache hit ratio for responding to the new data access requests;
receive a command to retrieve status of the integrated circuit memory dies; and
transmit the status information responsive to the command.