US 12,135,799 B2
Hardware storage unique key
Mark Trimmer, Coublevie (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Mar. 15, 2022, as Appl. No. 17/654,914.
Claims priority of application No. 2102718 (FR), filed on Mar. 18, 2021.
Prior Publication US 2022/0300624 A1, Sep. 22, 2022
Int. Cl. G06F 21/60 (2013.01); G06F 7/58 (2006.01)
CPC G06F 21/602 (2013.01) [G06F 7/588 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for operating an integrated circuit, the method comprising:
generating a random value by a random number generator circuit; and
storing the random value in a memory area of a non-volatile fuse-type memory by a finite state machine, the finite state machine coupled to the random number generator circuit via a first dedicated bus, the memory area being only accessible by the finite state machine,
wherein at each reset phase of the integrated circuit, a content of the memory area is loaded by the finite state machine into a volatile memory,
wherein a transition of the integrated circuit in and out of a state, allowing execution of a scan test, generates deleting of content stored in the volatile memory, and
wherein the non-volatile fuse-type memory is disconnected from the integrated circuit in response to the integrated circuit being in the state allowing execution of the scan test.